| Processor | Register Size | Bus Width | Addressable RAM | Description |
|---|---|---|---|---|
| 8086 | 16 | 16 | 1mb | 64k segmented memory model 220 = 1mb 20 pins for addressing |
| 8088 | 16 | 8 | 1mb | cheaper to manufacture activate/transmit |
| 80286 | 16 | 16 | 16mb | 2 operating modes 1. real mode (segmented) 2. protected (separated memory space segmentation faults 24 addressing pins introduced virtual memory (entire program does not have to be in RAM) |
| 80386-DX | 32 | 32 | 4gb | 3 operating modes: 1. real 2. protected 3. virtual-8086 (allows multiple DOS sessions) |
| 80386-SX | 32 | 16 | 4gb | cheaper due to competition (AMD & Cyrix) bad technology, but increased sales |
| 80486-DX | 32 | 32 | 7gb | added full pipelining added on-chip 8k cache (aka. L1 cache) integrated math coprocessor (aka. FPU, floating point unit) -DX2 doubled clock speed -DX4 tripled clock speed -SX doubled clock speed, removed FPU |
| Pentium/80586 | 32 | 64 | 4gb | dual integer units single FPU superscalar architecture separate 8k L1 caches for data & intructions |
| Pentium Pro | 32 | 64 | 64gb | 512k L2 cache (off-chip) L2 cache is a "prefetch to the prefetch" |
| Pentium II-MMX (Slot 1) | 32 | 64 | 64gb | L2 cache MMX - MultiMedia eXtendable or - Matrix Math eXtension registers in FPU for processing instructions faster SIMD - single instruction, multiple data |
| Pentium III | 32 | 64 | 64gb | faster clock speed |
68000
to
68040
competing chip - PowerPC